Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.11851/10670
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dc.contributor.authorKaramüftüoğlu, Mustafa Altay-
dc.contributor.authorBozbey, Ali-
dc.contributor.authorÖzbayoğlu, Murat-
dc.date.accessioned2023-10-24T06:59:07Z-
dc.date.available2023-10-24T06:59:07Z-
dc.date.issued2023-
dc.identifier.issn1051-8223-
dc.identifier.issn1558-2515-
dc.identifier.urihttps://doi.org/10.1109/TASC.2023.3295835-
dc.identifier.urihttps://hdl.handle.net/20.500.11851/10670-
dc.description.abstractArtificial neurons provide a new way of computation for neuro-inspired algorithms, and the abilities may efficiently solve the challenges. We propose implementations of logic gates (and, or, xor, and Majority), full adder, full subtractor, even parity generator, and 2-bit multiplier circuit formed by Josephson junction-based soma (JJ-Soma) and standard Rapid Single Flux Quantum (SFQ) digital library cells. The designed circuits execute ultra-high-speed operations without a clock signal, and they are capable of processing parallel or time-sliced operations. The combination of JJ-Soma cells and SFQ cells creates the potential models for the arithmetic logic unit devices with a small on-chip area, high operating speed, and pipeline structures for microprocessors. In this study, the previously optimized JJ-Soma circuits have low power consumption and high computational speed where the firing rates for two-pulse and three-pulse threshold circuits were designed to be 50 and 15 GHz with about 10(-19) J/spike energy level. The proposed circuits, fabricated with a commercial foundry service, have been implemented and demonstrated experimentally.en_US
dc.description.sponsorshipTUBITAK [121F266, 121E242]en_US
dc.description.sponsorshipThis work was supported by TUBITAK under Grant 121F266 and Grant 121E242. This article was recommended by Associate Editor Masamitsu Tanaka.& nbsp;en_US
dc.language.isoenen_US
dc.publisherIEEE-Inst Electrical Electronics Engineers Incen_US
dc.relation.ispartofIeee Transactions On Applied Superconductivityen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectArtificial somaen_US
dc.subjectfull adder (FA)en_US
dc.subjectJosephson junction-based soma (JJ-Soma)en_US
dc.subjectlogic gateen_US
dc.subjectmultiplieren_US
dc.subjectneural networken_US
dc.subjectparity circuiten_US
dc.subjectsuperconductoren_US
dc.titleImplementation of Neuro-Inspired Arithmetic and Logic Circuitsen_US
dc.typeArticleen_US
dc.departmentTOBB ETÜen_US
dc.identifier.volume33en_US
dc.identifier.issue7en_US
dc.identifier.wosWOS:001040003800002en_US
dc.identifier.scopus2-s2.0-85165242502en_US
dc.institutionauthor-
dc.identifier.doi10.1109/TASC.2023.3295835-
dc.authorscopusid57191445740-
dc.authorscopusid13606998800-
dc.authorscopusid57947593100-
dc.relation.publicationcategoryMakale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanıen_US
dc.identifier.scopusqualityQ2-
item.openairetypeArticle-
item.languageiso639-1en-
item.grantfulltextnone-
item.fulltextNo Fulltext-
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
item.cerifentitytypePublications-
crisitem.author.dept02.5. Department of Electrical and Electronics Engineering-
crisitem.author.dept02.1. Department of Artificial Intelligence Engineering-
Appears in Collections:Scopus İndeksli Yayınlar Koleksiyonu / Scopus Indexed Publications Collection
WoS İndeksli Yayınlar Koleksiyonu / WoS Indexed Publications Collection
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