Urfa-Update Based Register File Architecture With Partial Register Write for Energy Efficiency

Abstract

In modern architectures the register file is one of the most energy consuming and frequently used components of the processor. Therefore, reducing the register file power dissipation is critical. In this paper, we propose schemes that reduce the energy dissipation of the register file by not writing the bits that are not changed. Our schemes rely on the observation that on the average only 10% of the register bits are changed by the instructions. In this study, we propose a combination of architectural and circuit level techniques that exploit this inefficiency for the register file's write power reduction using an update based scheme. We show that for a 64-bit datapath it is possible to reduce the energy dissipation of the register file up to 25% for individual benchmark programs and by 21% on the average across all simulated benchmarks with a negligible performance compromise. (C) 2016 Elsevier B.V. All rights reserved.