Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.11851/1979
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dc.contributor.authorHassan, Hasan-
dc.contributor.authorPekhimenko, Gennady-
dc.contributor.authorVijaykumar, Nandita-
dc.contributor.authorSeshadri, Vivek-
dc.contributor.authorLee, Donghyuk-
dc.contributor.authorErgin, Oğuz-
dc.contributor.authorMutlu, Onur-
dc.date.accessioned2019-07-10T14:42:43Z
dc.date.available2019-07-10T14:42:43Z
dc.date.issued2016
dc.identifier.citationHassan, H., Pekhimenko, G., Vijaykumar, N., Seshadri, V., Lee, D., Ergin, O., & Mutlu, O. (2016, March). ChargeCache: Reducing DRAM latency by exploiting row access locality. In 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA) (pp. 581-593). IEEE.en_US
dc.identifier.isbn978-1-4673-9211-2
dc.identifier.issn1530-0897
dc.identifier.urihttps://ieeexplore.ieee.org/document/7446096-
dc.identifier.urihttps://hdl.handle.net/20.500.11851/1979-
dc.description22nd IEEE International Symposium on High-Performance Computer Architecture (HPCA) (2016 : Barcelona, SPAIN)
dc.description.abstractDRAM latency continues to be a critical bottleneck for system performance. In this work, we develop a low-cost mechanism, called ChargeCache, that enables faster access to recently-accessed rows in DRAM, with no modifications to DRAM chips. Our mechanism is based on the key observation that a recently-accessed row has more charge and thus the following access to the same row can be performed faster. To exploit this observation, we propose to track the addresses of recently-accessed rows in a table in the memory controller. If a later DRAM request hits in that table, the memory controller uses lower timing parameters, leading to reduced DRAM latency. Row addresses are removed from the table after a specified duration to ensure rows that have leaked too much charge are not accessed with lower latency. We evaluate ChargeCache on a wide variety of workloads and show that it provides significant performance and energy benefits for both single-core and multi-core systems.en_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.relation.ispartofInternational Symposium on High-Performance Computer Architecture-Proceedingsen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectDynamic random access storageen_US
dc.subjectData storage equipmenten_US
dc.subjectRefresh operationsen_US
dc.titleChargecache: Reducing Dram Latency by Exploiting Row Access Localityen_US
dc.typeConference Objecten_US
dc.departmentFaculties, Faculty of Engineering, Department of Computer Engineeringen_US
dc.departmentFakülteler, Mühendislik Fakültesi, Bilgisayar Mühendisliği Bölümütr_TR
dc.identifier.startpage581
dc.identifier.endpage593
dc.authorid0000-0003-2701-3787-
dc.identifier.wosWOS:000381808200048en_US
dc.identifier.scopus2-s2.0-84965013529en_US
dc.institutionauthorErgin, Oğuz-
dc.identifier.doi10.1109/HPCA.2016.7446096-
dc.authorwosidE-5717-2010-
dc.authorscopusid6603141208-
dc.relation.publicationcategoryKonferans Öğesi - Uluslararası - Kurum Öğretim Elemanıen_US
dc.identifier.scopusquality--
item.openairetypeConference Object-
item.languageiso639-1en-
item.grantfulltextnone-
item.fulltextNo Fulltext-
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
item.cerifentitytypePublications-
crisitem.author.dept02.3. Department of Computer Engineering-
Appears in Collections:Bilgisayar Mühendisliği Bölümü / Department of Computer Engineering
Scopus İndeksli Yayınlar Koleksiyonu / Scopus Indexed Publications Collection
WoS İndeksli Yayınlar Koleksiyonu / WoS Indexed Publications Collection
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