Demonstrating Reduced-Voltage FPGA-Based Neural Network Acceleration for Power-Efficiency

Abstract

This demo aims to demonstrate undervolting below the nominal level set by the vendor for off-the-shelf FPGAs running Deep Neural Networks (DNNs), to achieve power-efficiency. FPGAs are becoming popular [1-4], thanks to their higher throughput than GPUs and better flexibility than ASICs. To further improve the power-efficiency, we propose to employ undervolting below the nominal level (i.e., V_nom= 850mV for studied platform). FPGA vendors usually add a voltage guardband to ensure the correct operation under the worst-case circuit and environmental conditions [5-9]. However, these guardbands can be very conservative and unnecessary for state-of-the-art applications. Reducing the voltage in this guardband region does not lead to reliability issues under normal operating conditions, and thus, eliminating it can result in a significant power reduction for a wide variety of real-world applications. We will experimentally demonstrate a large voltage guardband for modern FPGAs: an average of 33%. Eliminating this guardband leads to significant power-efficiency (GOPs/W) improvement, on average, 2.6X, see Figure 1. © 2020 IEEE.