Please use this identifier to cite or link to this item:
https://hdl.handle.net/20.500.11851/6047
Title: | A 9.95-11.3-Gb/s XFP transceiver in 0.13-mu m CMOS | Authors: | Kenney, John G. Dalton, Declan Evans, Eric Eskiyerli, Murat Hayri Hilton, Barry Hitchcox, Dave DeVito, Lawrence |
Keywords: | clock and data recovery (CDR) delay-locked loop (DLL) frequency-locked loop (FLL) phase-locked loop (PLL) transceiver |
Publisher: | IEEE-Inst Electrical Electronics Engineers Inc | Abstract: | A 9.95-11.3-Gb/s transceiver in 0.13-mu m CMOS for XFP modules is presented. The CDR uses a dual-loop DLL/PLL with a binary phase detector to exceed XFP jitter specifications. The dual loop solves the problem of having a controlled jitter transfer bandwidth with a binary phase detector. A half rate binary phase detector with a 2:1 serializer implements full-rate I/O. Dispersion jitter from 12" of FR4 is equalized resulting in system JGEN under 4 mUI(RMs) and 35 mUI(PP). Power consumption is 800 mw. | URI: | https://doi.org/10.1109/JSSC.2006.884344 https://hdl.handle.net/20.500.11851/6047 |
ISSN: | 0018-9200 1558-173X |
Appears in Collections: | Bilgisayar Mühendisliği Bölümü / Department of Computer Engineering Scopus İndeksli Yayınlar Koleksiyonu / Scopus Indexed Publications Collection WoS İndeksli Yayınlar Koleksiyonu / WoS Indexed Publications Collection |
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