Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.11851/6688
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dc.contributor.authorKoçberber, Yusuf Onur-
dc.contributor.authorOsmanoğlu, Yusuf-
dc.contributor.authorErgin, Oğuz-
dc.date.accessioned2021-09-11T15:43:11Z-
dc.date.available2021-09-11T15:43:11Z-
dc.date.issued2009en_US
dc.identifier.issn1356-5362-
dc.identifier.urihttps://doi.org/10.1108/13565360910981526-
dc.identifier.urihttps://hdl.handle.net/20.500.11851/6688-
dc.description.abstractPurpose - The purpose of this paper is to reduce parity generation latency if the input value is narrow. Design/methodology/approach - Soft errors caused by cosmic particles and radiation emitted by the packaging are important problems in contemporary microprocessors. Parity bits are used to detect single bit errors that occur in the storage components. In order to implement parity logic, multiple levels of XOR gates are used and these XOR trees are known to have high delay. Many produced and consumed values inside a processor hold consecutive zeros and ones in their upper order bits. These values can be represented with less number of bits and hence are termed narrow. In this paper, a parity generator circuit design is proposed that is capable of generating parity it the input value is narrow. It is shown that the parity can be generated faster than a regular XOR tree implementation using this design for the values that can be represented using fewer bits. Findings - The proposed technique reduces the parity generation latency of 64-bit values by 50 percent for eight-bit narrow values. Considering the fact that around 70 percent of the immediate values written to the immediate field of the issue queue and around 40 percent of the value written to the integer register file can be expressed with only eight bits, the coverage of the proposed scheme is quite high. Originality/value - This paper shows the simulation results of fast parity generator circuit if the input value is narrow.en_US
dc.description.sponsorshipScientific and Technological Research Council of Turkey (TUBITAK)Turkiye Bilimsel ve Teknolojik Arastirma Kurumu (TUBITAK) [107E043]en_US
dc.description.sponsorshipThis work was supported in part by the Scientific and Technological Research Council of Turkey (TUBITAK) through research Grant 107E043.en_US
dc.language.isoenen_US
dc.publisherEmerald Group Publishing Limiteden_US
dc.relation.ispartofMicroelectronics Internationalen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectError analysisen_US
dc.subjectCodesen_US
dc.subjectCircuitsen_US
dc.titleExploiting Narrow Values for Faster Parity Generationen_US
dc.typeArticleen_US
dc.departmentFaculties, Faculty of Engineering, Department of Computer Engineeringen_US
dc.departmentFakülteler, Mühendislik Fakültesi, Bilgisayar Mühendisliği Bölümütr_TR
dc.identifier.volume26en_US
dc.identifier.issue3en_US
dc.identifier.startpage22en_US
dc.identifier.endpage29en_US
dc.authorid0000-0003-2701-3787-
dc.authorid0000-0002-9997-9479-
dc.identifier.wosWOS:000269050000003en_US
dc.identifier.scopus2-s2.0-70349237390en_US
dc.institutionauthorErgin, Oğuz-
dc.identifier.doi10.1108/13565360910981526-
dc.relation.publicationcategoryMakale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanıen_US
dc.identifier.scopusqualityQ4-
item.openairetypeArticle-
item.languageiso639-1en-
item.grantfulltextnone-
item.fulltextNo Fulltext-
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
item.cerifentitytypePublications-
crisitem.author.dept02.3. Department of Computer Engineering-
Appears in Collections:Bilgisayar Mühendisliği Bölümü / Department of Computer Engineering
Scopus İndeksli Yayınlar Koleksiyonu / Scopus Indexed Publications Collection
WoS İndeksli Yayınlar Koleksiyonu / WoS Indexed Publications Collection
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