Statistical Timing Analysis Tool for Sfq Cells (stats)

Abstract

Todays superconductor integrated circuits are increasingly taking part in various fields, such as processors, detector read-out systems and communication systems. As the circuit complexities increase, importance of robust and practical simulation software increases. However, at the moment, the tools used for circuit design are mostly made up by modifying the software used in the semiconductor technology. These tools generally doesn't consider the effects that may cause timing variances such as fabrication spread over design values and the thermal noise. Earlier studies show that timing variances become comparable with cell timings due to accumulation of timing jitter over long data transmission paths. It is possible to estimate these effects with analog simulators such as Jsim. However, due the number of simulations and simulation durations, it is not practical to use them for large circuits. At the moment, such large circuits are simulated with Verilog or similar simulators and each gate is modelled with only deterministic delay and interval values. Hence, these simulators only give an idea of the circuit operation with the assumption that all the timings are at the design value. In this work, we are developing a digital simulation tool for that can be used for large SFQ circuits with the assumption that the constituting gates have probabilistic, mainly Gaussian, output distributions. Our simulator also gives the output probabilities for the circuits and individual gates.