Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.11851/9250
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dc.contributor.authorGiray, Yaglikci, A.-
dc.contributor.authorOlgun, A.-
dc.contributor.authorPatel, M.-
dc.contributor.authorLuo, H.-
dc.contributor.authorHassan, H.-
dc.contributor.authorOrosa, L.-
dc.contributor.authorErgin, Oğuz-
dc.date.accessioned2022-11-30T19:37:38Z-
dc.date.available2022-11-30T19:37:38Z-
dc.date.issued2022-
dc.identifier.isbn9781665462723-
dc.identifier.issn1072-4451-
dc.identifier.urihttps://doi.org/10.1109/MICRO56248.2022.00062-
dc.identifier.urihttps://hdl.handle.net/20.500.11851/9250-
dc.descriptionaws;et al.;Futurewei Technologies;IBM;Intel;Northwestern Engineeringen_US
dc.description55th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2022 -- 1 October 2022 through 5 October 2022 -- 183812en_US
dc.description.abstractDRAM is the building block of modern main memory systems. DRAM cells must be periodically refreshed to prevent data loss. Refresh operations degrade system performance by interfering with memory accesses. As DRAM chip density increases with technology node scaling, refresh operations also increase be-cause: 1) the number of DRAM rows in a chip increases; and 2) DRAM cells need additional refresh operations to mitigate bit failures caused by RowHammer, a failure mechanism that becomes worse with technology node scaling. Thus, it is critical to enable refresh operations at low performance overhead. To this end, we propose a new operation, Hidden Row Activation (HiRA), and the HiRA Memory Controller (HiRA-MC) to perform HiRA operations. HiRA hides a refresh operation's latency by refreshing a row concurrently with accessing or refreshing another row within the same bank. Unlike prior works, HiRA achieves this parallelism without any modifications to off-the-shelf DRAM chips. To do so, it leverages the new observation that two rows in the same bank can be activated without data loss if the rows are connected to different charge restoration circuitry. We experimentally demonstrate on 56 real off-the-shelf DRAM chips that HiRA can reliably parallelize a DRAM row's refresh operation with refresh or activation of any of the 32% of the rows within the same bank. By doing so, HiRA reduces the overall latency of two refresh operations by 51.4%. HiRA-MC modifies the memory request scheduler to perform HiRA when a refresh operation can be performed concurrently with a memory access or another refresh. Our system-level evaluations show that HiRA-MC increases system performance by 12.6% and 3.73× as it reduces the performance degradation due to periodic refreshes and refreshes for RowHammer protection (preventive refreshes), respectively, for future DRAM chips with increased density and RowHammer vulnerability. © 2022 IEEE.en_US
dc.language.isoenen_US
dc.publisherIEEE Computer Societyen_US
dc.relation.ispartofProceedings of the Annual International Symposium on Microarchitecture, MICROen_US
dc.rightsinfo:eu-repo/semantics/openAccessen_US
dc.subjectDRAMen_US
dc.subjectmemory access latencyen_US
dc.subjectmemory controlleren_US
dc.subjectrefreshen_US
dc.subjectrowhammeren_US
dc.subjectDynamic random access storageen_US
dc.subjectFailure (mechanical)en_US
dc.subjectMemory architectureen_US
dc.subjectData lossen_US
dc.subjectDRAM cellsen_US
dc.subjectDRAM chipsen_US
dc.subjectMemory accessen_US
dc.subjectMemory access latencyen_US
dc.subjectMemory controlleren_US
dc.subjectRefreshen_US
dc.subjectRowhammeren_US
dc.subjectSystems performanceen_US
dc.subjectTechnology nodesen_US
dc.subjectChemical activationen_US
dc.titleHira: Hidden Row Activation for Reducing Refresh Latency of Off-The Dram Chipsen_US
dc.typeConference Objecten_US
dc.identifier.volume2022-Octoberen_US
dc.identifier.startpage815en_US
dc.identifier.endpage834en_US
dc.identifier.wosWOS:000886530600048en_US
dc.identifier.scopus2-s2.0-85141681064en_US
dc.institutionauthorErgin, Oğuz-
dc.identifier.doi10.1109/MICRO56248.2022.00062-
dc.authorscopusid57219630381-
dc.authorscopusid57222238840-
dc.authorscopusid57193929158-
dc.authorscopusid57219265788-
dc.authorscopusid57189066886-
dc.authorscopusid55062282700-
dc.authorscopusid6603141208-
dc.relation.publicationcategoryKonferans Öğesi - Uluslararası - Kurum Öğretim Elemanıen_US
dc.identifier.scopusquality--
dc.ozel2022v3_Editen_US
item.openairetypeConference Object-
item.languageiso639-1en-
item.grantfulltextnone-
item.fulltextNo Fulltext-
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
item.cerifentitytypePublications-
crisitem.author.dept02.3. Department of Computer Engineering-
Appears in Collections:Bilgisayar Mühendisliği Bölümü / Department of Computer Engineering
Scopus İndeksli Yayınlar Koleksiyonu / Scopus Indexed Publications Collection
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