Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.11851/6729
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dc.contributor.authorChang, Kevin K.-
dc.contributor.authorKashyap, Abhijith-
dc.contributor.authorHassan, Hasan-
dc.contributor.authorGhose, Saugata-
dc.contributor.authorHsieh, Kevin-
dc.contributor.authorLee, Donghyuk-
dc.contributor.authorMutlu, Onur-
dc.date.accessioned2021-09-11T15:43:20Z-
dc.date.available2021-09-11T15:43:20Z-
dc.date.issued2018en_US
dc.identifier.issn1820-4503-
dc.identifier.urihttps://hdl.handle.net/20.500.11851/6729-
dc.description.abstractThis article summarizes key results of our work on experimental characterization and analysis of latency variation and latency-reliability trade-offs in modern DRAM chips, which was published in SIGMETRICS 2016 [ 24], and examines the work's signifficance and future potential. Our work is motivated to reduce the long DRAM latency, which is a critical performance bottleneck in current systems. DRAM access latency is defined by three fundamental operations that take place within the DRAM cell array: (i) activation of a memory row, which opens the row to perform accesses; (ii) precharge, which prepares the cell array for the next memory access; and (iii) restoration of the row, which restores the values of cells in the row that were destroyed due to activation. There is significant latency variation for each of these operations across the cells of a single DRAM chip due to irregularity in the manufacturing process. As a result, some cells are inherently faster to access, while others are inherently slower. Unfortunately, existing systems do not exploit this variation. The goal of this work is to (i) experimentally characterize and understand the latency variation across cells within a DRAM chip for these three fundamental DRAM operations, and (ii) develop new mechanisms that exploit our understanding of the latency variation to reliably improve performance. To this end, we comprehensively characterize 240 DRAM chips from three major vendors, and make six major new observations about latency variation within DRAM. Notably, we find that (i) there is large latency variation across the cells for each of the three operations; (ii) variation characteristics exhibit significant spatial locality: slower cells are clustered in certain regions of a DRAM chip; and (iii) the three fundamental operations exhibit different reliability characteristics when the latency of each operation is reduced. Based on our observations, we propose Flexible-LatencY DRAM (FLY-DRAM), a mechanism that exploits latency variation across DRAM cells within a DRAM chip to improve system performance. The key idea of FLY-DRAM is to exploit the spatial locality of slower cells within DRAM, and access the faster DRAM regions with reduced latencies for the fundamental operations. Our evaluations show that FLY-DRAM improves the performance of a wide range of applications by 13.3%, 17.6%, and 19.5%, on average, for each of the three different vendors' real DRAM chips, in a simulated 8-core system. We have open sourced the data from our research online. We hope the characterization and analysis we provide opens up new research directions for both researchers and practitioners in computer architecture and systems.en_US
dc.description.sponsorshipGoogleGoogle Incorporated; IntelIntel Corporation; NVIDIA; SamsungSamsung; ISTC-CC; SRC; NSFNational Science Foundation (NSF) [1212962, 1320531]; SRCEA/Intel Fellowshipen_US
dc.description.sponsorshipWe thank the anonymous reviewers and SAFARI group members for their feedback. We acknowledge the support of Google, Intel, NVIDIA, and Samsung. This research was supported in part by the ISTC-CC, SRC, and NSF (grants 1212962 and 1320531). Kevin Chang was supported in part by the SRCEA/Intel Fellowship.en_US
dc.language.isoenen_US
dc.publisherIpsi Belgrade Ltden_US
dc.relation.ispartofIpsi Bgd Transactions On Internet Researchen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subject[No Keywords]en_US
dc.titleFlexible-Latency DRAM: Understanding and Exploiting Latency Variation in Modern DRAM Chipsen_US
dc.typeArticleen_US
dc.departmentFaculties, Faculty of Engineering, Department of Computer Engineeringen_US
dc.departmentFakülteler, Mühendislik Fakültesi, Bilgisayar Mühendisliği Bölümütr_TR
dc.identifier.volume14en_US
dc.identifier.issue2en_US
dc.authorid0000-0003-4154-4525-
dc.identifier.wosWOS:000458407800004en_US
dc.institutionauthorHassan, Hasan-
dc.relation.publicationcategoryMakale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanıen_US
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
item.languageiso639-1en-
item.cerifentitytypePublications-
item.fulltextNo Fulltext-
item.grantfulltextnone-
item.openairetypeArticle-
Appears in Collections:Bilgisayar Mühendisliği Bölümü / Department of Computer Engineering
WoS İndeksli Yayınlar Koleksiyonu / WoS Indexed Publications Collection
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