Browsing by Author "Fujimaki, Akira"

Now showing 1 - 7 of 7

Citation - WoS: 1
Demonstration of Individual Readout of Serially-Connected Superconducting Strip Line Detectors
(IEEE, 2015) Kamiya, Kyohei; Kita, Yuma; Kozaka, Misaki; Tanaka, Masamitsu; Fujimaki, Akira; Bozbey, Ali
We report successful demonstration of individual readout of the response to an optical signal in serially-connected superconducting strip line detectors (SSLDs). Based on the numerical analysis, placement of low-pass filters between adjacent SSLDs and use of a current-source drive enable serially-connected SSLDs to work as independent multiple SSLDs. This leads to reduction of the number of cables from room temperature electronics. We irradiate a laser just on a certain SSLD (SSLD#1) with On/Off modulation. Synchronized voltage output is obtained at only corresponding SQUID. Then we move the position of a laser spot on the neighbor SSLD (SSLD#2). The voltage disappears at the SQUID connecting to SSLD#1, and the voltage is developed only at the SQUID connecting to SSLD#2. We have also given a demonstration of readout using the singleflux-quantum circuits connected to the SQUIDs. We confirmed from those experimental results that our driving method for multiple SSLDs is effective not only to enhance detecting area but also to obtain position sensitivity.
Citation - WoS: 3
Citation - Scopus: 2
Development of an Advanced Circuit Model for Superconducting Strip Line Detector Arrays
(IEICE-Inst Electronics Information Communications Eng, 2016) Bozbey, Ali; Kita, Yuma; Kamiya, Kyohei; Kozaka, Misaki; Tanaka, Masamitsu; Ishida, Takekazu; Fujimaki, Akira
One of the fundamental problems in many-pixel detectors implemented in cryogenics environments is the number of bias and read-out wires. If one targets a megapixel range detector, number of wires should be significantly reduced. One possibility is that the detectors are serially connected and biased by using only one line and read-out is accomplished by on-chip circuitry. In addition to the number of pixels, the detectors should have fast response times, low dead times, high sensitivities, low inter-pixel crosstalk and ability to respond to simultaneous irradiations to individual pixels for practical purposes. We have developed an equivalent circuit model for a serially connected superconducting strip line detector (SSLD) array together with the read-out electronics. In the model we take into account the capacitive effects due to the ground plane under the detector, effects of the shunt resistors fabricated under the SSLD layer, low pass filters placed between the individual pixels that enable individual operation of each pixel and series resistors that prevents the DC bias current flowing to the read-out electronics as well as adjust the time constants of the inductive SSLD loop. We explain the results of investigation of the following parameters: Crosstalk between the neighbor pixels, response to simultaneous irradiation, dead times, L/R time constants, low pass filters, and integration with the SFQ front-end circuit. Based on the simulation results, we show that SSLDs are promising devices for detecting a wide range of incident radiation such as neurons, X-rays and THz waves in many-pixel configurations.
Citation - WoS: 5
Citation - Scopus: 7
Development of an Optimizer for Vortex Transitional Memory Using Particle Swarm Optimization
(IEEE-Inst Electrical Electronics Engineers Inc, 2016-12) Karamüftüoğlu, Mustafa Altay; Demirhan, Seda; Komura, Yuto; Çelik, Mustafa Eren; Tanaka, Masamitsu; Bozbey, Ali; Fujimaki, Akira
High-performance computing that involves superconducting digital circuits is one of the promising technologies. A number of groups have already demonstrated working prototypes of CPUs or ALUs. However, one of the bottlenecks of these circuits is that it is very difficult to have large memories with very high speed and low-power consumption. One of the potential candidates compatible with the already available superconducting foundries that might enable on-chip memory is the vortex transitional memory (VTM) cell. However, VTM operation is mainly based on dc I/O rather than single-flux quantum I/O. VTM cell is mainly based on four Josephson junctions and it is a relatively simple circuit. Nevertheless, optimization of such a cell is a hectic process, as VTM cells are not used as a single cell but combined all together inside a connected network. In this study, we report an optimizer that uses particle swarm optimization algorithm and the results of optimization of VTM cells. By starting from random circuit parameters, the optimizer is able to converge on a working set of parameters fabricated using AIST standard process 2 and advanced process 2 processes with a minimum margin of +/- 30% and +/- 15%, respectively. Optimizations are completed in less than 100 h on a 12-core computer. Fabricated VTM cells have 15% operation margin.
Citation - WoS: 4
Citation - Scopus: 5
Experimental Demonstration and Numerical Analysis of Microampere Gray Zone Width With Enhanced Operating Margin in Shunted Quasi-One Junction Superconducting Quantum Interference Device Comparators
(Japan Soc Applied Physics, 2013) Miyajima, Shigeyuki; Ortlepp, Thomas; Toepfer, Hannes; Bozbey, Ali; Fujimaki, Akira
We evaluated the relationship between the gray zone width and the operating margin for comparators composed of quasi-one-junction superconducting quantum interference devices (QOSs) with shunt resistors, which are often used as high-speed readout circuits in multiple superconductor detector systems. The gray zone width is a good measure of current sensitivity of a single-bit comparator. We numerically analyzed the gray zone width of a QOS comparator and determined the circuit parameters. The gray zone width obtained from the experiments concurred with the results of the numerical analysis and was 2-3 mu A at 4.2 K in a QOS comparator composed of three Nb/AlOx/Nb junctions with critical currents of less than 90 mu A. The experimentally obtained operating margin for the bias current provided to the comparator was +/- 15% at the bias current of around 140 mu A. These results show that QOS comparators are promising for readout circuits operating up to tens of GHz and imply that gray zone width is the thermal noise in the resistors at 4.2 K. (c) 2013 The Japan Society of Applied Physics
Citation - WoS: 3
Citation - Scopus: 5
Sfq Parallel Encoders Promising for Video Imaging With Superconductor Stripline Detectors
(IEEE-Inst Electrical Electronics Engineers Inc, 2021) Tanaka, Masamitsu; Kozaka, Misaki; Kamiya, Kyohei; Üşenmez, Kubra; Aydoğan, Eren Can; Razmkhah, Sasan; Fujimaki, Akira
We report demonstration of a readout circuit with high-throughput single flux quantum (SFQ) based encoders for a large-scale video imaging system with a conventional frame rate. The encoders are fully parallel and integrated on the same chip as linear arrays of serially connected superconductor stripline detectors (SSLDs), superconducting quantum interference device (SQUID) based comparators, and SFQ synchronizers. Mutual coupling of parallel SSLDs and SQUID-based comparators allows the use of only one dc bias line; it is possible to use thousands of SSLDs without increasing the bias current or number of bias ports. To achieve crosstalk-free readout, the serially connected SSLDs are separated by low-pass filters or large inductors. We experimentally demonstrated crosstalk-free readout including SFQ parallel encoders from 1-D or 2-D serially connected SSLD arrays.
Citation - WoS: 2
Citation - Scopus: 2
Synchronous SFQ Address Encoder for Superconductor Detector Arrays
(IEEE-Inst Electrical Electronics Engineers Inc, 2021) Bozbey, Ali; Aydoğan, Eren; Üşenmez, Kübra; Razmkhah, Sasan; Tanaka, Masamitsu; Fujimaki, Akira
With the advances in superconductor detectors and single flux quantum (SFQ) logic circuits, megapixel imagers have become possible. Various detectors such as superconducting stripline detectors (SSLD), kinetic inductance detectors, nanowire single-photon detectors have quite matured in terms of speed and performance. However, scaling of the read-out electronics is still a challenge. We propose an SFQ based synchronous address encoder to read-out the response of an SSLD array. The encoder circuit provides two sets of outputs at each clock period: one is the time-division multiplexed, serial data output, and the other is the synchronized address output associated with the time-multiplexed data. Thus, the number of connections to the room temperature is substantially reduced. We experimentally demonstrate a 2-bit encoder. Then, we present the scalability of the circuit to larger arrays and show the simulation results of a 4-bit encoder, which is suitable to read-out a 16 x 16 detector array.
Citation - WoS: 2
Citation - Scopus: 4
Vortex Transitional Memory Developed With Nb 4-Layer, 10-ka/Cm(2) Fabrication Process
(IEEE, 2015) Komura, Yuto; Tanaka, Masamitsu; Fujimaki, Akira; Nagasawa, Shuichi; Bozbey, Ali
We report random access memories (RAMs) based on vortex transitional (VT) memory cell developed with the newly developed AIST 10-kA/cm(2), Nb 4-layer fabrication process, called High-Speed Standard Process (HSTP). We obtained more effective mutual coupling structure by fully use of all the wiring layer, and successfully reduced the cell size to 25 mu m square, which indicated roughly 50% increase in density compared to the previous design. We reduced the critical currents of Josephson junctions and load resistance to be matched with driving circuitry. We tested the miniaturized VT memory cell, and obtained a sufficient margin width of similar to 15%, and also confirmed correct operations of the other components, including a latching driver and address decoder.