A Statistical Approach To Delay, Jitter and Timing of Signals of Rsfq Wiring Cells and Clocked Gates

Abstract

Rapid single flux quantum technology is one of the most promising developments for future high-speed microprocessors, network routers, and analog-to-digital converters. This technology is based on well-timed signals and fast signal transmission. However, as the complexity of the circuits or the operating frequency of these signals increase, it becomes harder to achieve a successful timing scheme. Another case that prevents successful timing is thermal noise, which becomes more significant with the increase of the number of cells. Earlier studies on noise analysis show that the timing variations of the delay on a cascaded path vary up to 10% compared with the delay of the same type of single cell. On the other hand, circuit parameters may change during the fabrication process, and as a result, timing of the cell differs from the design value. For these reasons, we define a statistical model for the wiring cells, such as Josephson transmission lines, splitters, and mergers that can be used to calculate the timing delay and jitter instead of time-consuming simulations. We also discuss a possible method to identify the sensitive paths to the delay fluctuations among different alternatives. In this study, we analyze the delay and the jitter of cascaded combinations of the most common wiring cells to determine the correlation effect on delay and jitter between the consecutive gates. Then, we propose a statistical method to analyze these timings faster and easier. Finally, we discussed how to estimate the output probability of the clocked gates without performing an actual simulation.