Vortex Transitional Memory Developed With Nb 4-Layer, 10-ka/Cm(2) Fabrication Process

Abstract

We report random access memories (RAMs) based on vortex transitional (VT) memory cell developed with the newly developed AIST 10-kA/cm(2), Nb 4-layer fabrication process, called High-Speed Standard Process (HSTP). We obtained more effective mutual coupling structure by fully use of all the wiring layer, and successfully reduced the cell size to 25 mu m square, which indicated roughly 50% increase in density compared to the previous design. We reduced the critical currents of Josephson junctions and load resistance to be matched with driving circuitry. We tested the miniaturized VT memory cell, and obtained a sufficient margin width of similar to 15%, and also confirmed correct operations of the other components, including a latching driver and address decoder.