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https://hdl.handle.net/20.500.11851/10670
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DC Field | Value | Language |
---|---|---|
dc.contributor.author | Karamüftüoğlu, Mustafa Altay | - |
dc.contributor.author | Bozbey, Ali | - |
dc.contributor.author | Özbayoğlu, Murat | - |
dc.date.accessioned | 2023-10-24T06:59:07Z | - |
dc.date.available | 2023-10-24T06:59:07Z | - |
dc.date.issued | 2023 | - |
dc.identifier.issn | 1051-8223 | - |
dc.identifier.issn | 1558-2515 | - |
dc.identifier.uri | https://doi.org/10.1109/TASC.2023.3295835 | - |
dc.identifier.uri | https://hdl.handle.net/20.500.11851/10670 | - |
dc.description.abstract | Artificial neurons provide a new way of computation for neuro-inspired algorithms, and the abilities may efficiently solve the challenges. We propose implementations of logic gates (and, or, xor, and Majority), full adder, full subtractor, even parity generator, and 2-bit multiplier circuit formed by Josephson junction-based soma (JJ-Soma) and standard Rapid Single Flux Quantum (SFQ) digital library cells. The designed circuits execute ultra-high-speed operations without a clock signal, and they are capable of processing parallel or time-sliced operations. The combination of JJ-Soma cells and SFQ cells creates the potential models for the arithmetic logic unit devices with a small on-chip area, high operating speed, and pipeline structures for microprocessors. In this study, the previously optimized JJ-Soma circuits have low power consumption and high computational speed where the firing rates for two-pulse and three-pulse threshold circuits were designed to be 50 and 15 GHz with about 10(-19) J/spike energy level. The proposed circuits, fabricated with a commercial foundry service, have been implemented and demonstrated experimentally. | en_US |
dc.description.sponsorship | TUBITAK [121F266, 121E242] | en_US |
dc.description.sponsorship | This work was supported by TUBITAK under Grant 121F266 and Grant 121E242. This article was recommended by Associate Editor Masamitsu Tanaka.& nbsp; | en_US |
dc.language.iso | en | en_US |
dc.publisher | IEEE-Inst Electrical Electronics Engineers Inc | en_US |
dc.relation.ispartof | Ieee Transactions On Applied Superconductivity | en_US |
dc.rights | info:eu-repo/semantics/closedAccess | en_US |
dc.subject | Artificial soma | en_US |
dc.subject | full adder (FA) | en_US |
dc.subject | Josephson junction-based soma (JJ-Soma) | en_US |
dc.subject | logic gate | en_US |
dc.subject | multiplier | en_US |
dc.subject | neural network | en_US |
dc.subject | parity circuit | en_US |
dc.subject | superconductor | en_US |
dc.title | Implementation of Neuro-Inspired Arithmetic and Logic Circuits | en_US |
dc.type | Article | en_US |
dc.department | TOBB ETÜ | en_US |
dc.identifier.volume | 33 | en_US |
dc.identifier.issue | 7 | en_US |
dc.identifier.wos | WOS:001040003800002 | en_US |
dc.identifier.scopus | 2-s2.0-85165242502 | en_US |
dc.institutionauthor | … | - |
dc.identifier.doi | 10.1109/TASC.2023.3295835 | - |
dc.authorscopusid | 57191445740 | - |
dc.authorscopusid | 13606998800 | - |
dc.authorscopusid | 57947593100 | - |
dc.relation.publicationcategory | Makale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanı | en_US |
dc.identifier.scopusquality | Q2 | - |
item.fulltext | No Fulltext | - |
item.grantfulltext | none | - |
item.cerifentitytype | Publications | - |
item.openairecristype | http://purl.org/coar/resource_type/c_18cf | - |
item.openairetype | Article | - |
item.languageiso639-1 | en | - |
crisitem.author.dept | 02.5. Department of Electrical and Electronics Engineering | - |
crisitem.author.dept | 02.1. Department of Artificial Intelligence Engineering | - |
Appears in Collections: | Scopus İndeksli Yayınlar Koleksiyonu / Scopus Indexed Publications Collection WoS İndeksli Yayınlar Koleksiyonu / WoS Indexed Publications Collection |
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