Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.11851/10676
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dc.contributor.authorBolata, Alperen-
dc.contributor.authorTuğrul, Yahya Can-
dc.contributor.authorÇelik, Seyyid Hikmet-
dc.contributor.authorSezer, Şakir-
dc.contributor.authorOttavi, Marco-
dc.contributor.authorErgin, Oğuz-
dc.date.accessioned2023-10-24T06:59:09Z-
dc.date.available2023-10-24T06:59:09Z-
dc.date.issued2023-
dc.identifier.isbn979-8-3503-3634-4-
dc.identifier.issn1530-1877-
dc.identifier.urihttps://doi.org/10.1109/ETS56758.2023.10174063-
dc.identifier.urihttps://hdl.handle.net/20.500.11851/10676-
dc.description28th IEEE European Test Symposium (ETS) -- MAY 22-26, 2023 -- Venice, ITALYen_US
dc.description.abstractInstruction injections or soft errors during execution on the CPU can cause serious system vulnerabilities. During the standard program flow of the processor, the injection of unauthorized instruction or the occurrence of an error in the expected instruction are the main conditions for potentially serious such vulnerabilities. With the execution of these unauthorized instructions, adversaries could exploit SoC and execute their own malicious program or get higher-level privileges on the system. On the other hand, non-intentional errors can potentially corrupt programs causing unintended executions or the cause of program crashes. Modern trusted architectures propose solutions for unauthorized execution on SoC with additional software mechanisms or extra hardware logic on the same untrusted SoC. Nevertheless, these SoCs can still be vulnerable, as long as deployed security detection mechanisms are embedded within the same SoC's fabric. Furthermore, validation mechanisms on the SoC increase the complexity and power consumption of the SoC. This paper presents DEV-PIM, a new, high-performance, and low-cost execution validation mechanism in SoCs with external DRAM memory. The proposed approach uses processingin-memory (PIM) method to detect instruction injections or corrupted instructions by utilising basic computing resources on a standard DRAM device. DEV-PIM transfers instructions scheduled for execution on the CPU to the DRAM and validates them by comparing content with the trusted program record on the DRAM using PIM operations. By optimising the DRAM scheduling process validation tasks are only executed when memory access is idle. The CPU retains uninterrupted memory access and can continue its normal program flow without penalty. We evaluate DEV-PIM in an end-to-end DRAM-compatible environment and run a set of software benchmarks. On average, the proposed architecture is able to detect 98.46% of instruction injections for different validation. We also measured on average only 0.346% CPU execution overhead with DEV-PIM enabled.en_US
dc.description.sponsorshipIEEE,IEEE Comp Soc,IEEE Council Electron Design Automat,IEEE Comp Soc Test Technol Tech Council,CNRS,Ecole Centrale Lyon,Politecnico Torinoen_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.relation.ispartof2023 Ieee European Test Symposium, Etsen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectExecution Validationen_US
dc.subjectDRAMen_US
dc.subjectProcessing-in-Memoryen_US
dc.subjectTrusted Executionen_US
dc.titleDEV-PIM: Dynamic Execution Validation with Processing-in-Memoryen_US
dc.typeConference Objecten_US
dc.departmentTOBB ETÜen_US
dc.identifier.wosWOS:001032757100024en_US
dc.identifier.scopus2-s2.0-85166178144en_US
dc.institutionauthor-
dc.identifier.doi10.1109/ETS56758.2023.10174063-
dc.authorscopusid57216901758-
dc.authorscopusid57322480300-
dc.authorscopusid57815948000-
dc.authorscopusid7004935772-
dc.authorscopusid23482610400-
dc.authorscopusid6603141208-
dc.relation.publicationcategoryKonferans Öğesi - Uluslararası - Kurum Öğretim Elemanıen_US
item.fulltextNo Fulltext-
item.grantfulltextnone-
item.cerifentitytypePublications-
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
item.openairetypeConference Object-
item.languageiso639-1en-
crisitem.author.dept02.3. Department of Computer Engineering-
Appears in Collections:Scopus İndeksli Yayınlar Koleksiyonu / Scopus Indexed Publications Collection
WoS İndeksli Yayınlar Koleksiyonu / WoS Indexed Publications Collection
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