Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.11851/1154
Title: Exploiting processor features to implement error detection in reduced precision matrix multiplications
Authors: Reviriego, Pedro
Can, Serdar Zafer
Eryılmaz, Çağrı
Antonio Maestro, Juan
Ergin, Oğuz
143001
Keywords: Matrix Multiplication
Error Detection
Soft Errors
Issue Date: Aug-2014
Publisher: Elsevier
Source: Reviriego, P., Can, S. Z., Eryılmaz, Ç., Maestro, J. A., & Ergin, O. (2014). Exploiting processor features to implement error detection in reduced precision matrix multiplications. Microprocessors and Microsystems, 38(6), 581-584.
Abstract: Modern processors incorporate complex arithmetic units that can work with large word-lengths. Those units are useful for applications that require high precision. There are however, many applications for which the use of reduced precision is sufficient. In those cases, one possibility is to use the large word-length arithmetic units to implement reduced precision operations with additional error detection. In this paper, this idea is explored for the case of matrix multiplications. A technique is presented and evaluated. The results show that it can detect most errors and that for large matrixes the overhead in terms of execution time is small. (C) 2014 Elsevier B.V. All rights reserved.
URI: https://www.sciencedirect.com/science/article/pii/S0141933114000726?via%3Dihub
https://hdl.handle.net/20.500.11851/1154
ISSN: 0141-9331
Appears in Collections:Bilgisayar Mühendisliği Bölümü / Department of Computer Engineering
Scopus İndeksli Yayınlar Koleksiyonu / Scopus Indexed Publications Collection
WoS İndeksli Yayınlar Koleksiyonu / WoS Indexed Publications Collection

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