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https://hdl.handle.net/20.500.11851/12487
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DC Field | Value | Language |
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dc.contributor.author | Tugrul, Yahya Can | - |
dc.contributor.author | Yaglikci, A. Giray | - |
dc.contributor.author | Yuksel, Ismail Emir | - |
dc.contributor.author | Olgun, Ataberk | - |
dc.contributor.author | Canpolat, Oguzhan | - |
dc.contributor.author | Bostanci, Nisa | - |
dc.contributor.author | Mutlu, Onur | - |
dc.date.accessioned | 2025-05-10T19:34:54Z | - |
dc.date.available | 2025-05-10T19:34:54Z | - |
dc.date.issued | 2025 | - |
dc.identifier.isbn | 9798331506483 | - |
dc.identifier.isbn | 9798331506476 | - |
dc.identifier.issn | 1530-0897 | - |
dc.identifier.uri | https://doi.org/10.1109/HPCA61900.2025.00070 | - |
dc.description | Ergin, Oguz/0000-0003-2701-3787 | en_US |
dc.description.abstract | Read disturbance in modern DRAM chips is a widespread weakness that is used for breaking memory isolation, one of the fundamental building blocks of system security and privacy. RowHammer is a prime example of read disturbance in DRAM where repeatedly accessing (hammering) a row of DRAM cells (DRAM row) induces bitflips in physically nearby DRAM rows (victim rows). Unfortunately, shrinking technology node size exacerbates RowHammer and as such, significantly fewer accesses can induce bitflips in newer DRAM chip generations. To ensure robust DRAM operation, state-of-the-art mitigation mechanisms restore the charge in potential victim rows (i.e., they perform preventive refresh or charge restoration). With newer DRAM chip generations, these mechanisms perform preventive refresh more aggressively and cause larger performance, energy, or area overheads. Therefore, it is essential to develop a better understanding and in-depth insights into the preventive refresh to secure real DRAM chips at low cost. In this paper, our goal is to mitigate RowHammer at low cost by understanding the preventive refresh latency and the impact of reduced refresh latency on RowHammer. To this end, we present the first rigorous experimental study on the interactions between refresh latency and RowHammer characteristics in real DRAM chips. Our experimental characterization using 388 real DDR4 DRAM chips from three major manufacturers demonstrates that a preventive refresh latency can be significantly reduced (by 64%) at the expense of requiring slightly more (by 0.54%) preventive refreshes. To investigate the impact of reduced preventive refresh latency on system performance and energy efficiency, we reduce the preventive refresh latency and adjust the aggressiveness of existing RowHammer solutions by developing a new mechanism, Partial Charge Restoration for Aggressive Mitigation (PaCRAM). Our results show that by reducing the preventive refresh latency, PaCRAM reduces the performance and energy overheads induced by five state-of-the-art RowHammer mitigation mechanisms with small additional area overhead. Thus, PaCRAM introduces a novel perspective into addressing RowHammer vulnerability at low cost by leveraging our experimental observations. To aid future research, we open-source our PaCRAM implementation at https://github.com/CMU- SAFARI/PaCRAM. | en_US |
dc.description.sponsorship | Google Security and Privacy Research Award; Microsoft Swiss Joint Research Center; ETH Future Computing Laboratory; Google; Huawei; Intel; Microsoft; VMware | en_US |
dc.description.sponsorship | We thank the anonymous reviewers of HPCA 2025 (both main submission and artifact evaluation), MICRO 2024, and ISCA 2024 for the encouraging feedback. We thank the SAFARI Research Group members for valuable feedback and the stimulating scientific and intellectual environment. We acknowledge the generous gift funding provided by our industrial partners (especially Google, Huawei, Intel, Microsoft, VMware), which has been instrumental in enabling the research we have been conducting on read disturbance in DRAM since 2011 [3]. This work was also in part supported by the Google Security and Privacy Research Award, the Microsoft Swiss Joint Research Center, and the ETH Future Computing Laboratory (EFCL). | en_US |
dc.language.iso | en | en_US |
dc.publisher | IEEE Computer Soc | en_US |
dc.relation.ispartof | 2025 International Symposium on High Performance Computer Architecture-HPCA-Annual -- MAR 01-05, 2025 -- Las Vegas, NV | en_US |
dc.rights | info:eu-repo/semantics/closedAccess | en_US |
dc.title | Understanding Rowhammer Under Reduced Refresh Latency: Experimental Analysis of Real Dram Chips and Implications on Future Solutions | en_US |
dc.type | Conference Object | en_US |
dc.relation.ispartofseries | International Symposium on High-Performance Computer Architecture-Proceedings | - |
dc.department | TOBB University of Economics and Technology | en_US |
dc.identifier.startpage | 867 | en_US |
dc.identifier.endpage | 886 | en_US |
dc.authorid | Ergin, Oguz/0000-0003-2701-3787 | - |
dc.identifier.wos | WOS:001494383800062 | - |
dc.identifier.scopus | 2-s2.0-105003388361 | - |
dc.identifier.doi | 10.1109/HPCA61900.2025.00070 | - |
dc.authorwosid | Yüksel, İsmail Emir/Grj-1043-2022 | - |
dc.authorwosid | Ergin, Oguz/E-5717-2010 | - |
dc.relation.publicationcategory | Konferans Öğesi - Uluslararası - Kurum Öğretim Elemanı | en_US |
dc.identifier.scopusquality | N/A | - |
dc.identifier.wosquality | N/A | - |
dc.description.woscitationindex | Conference Proceedings Citation Index - Science | - |
item.languageiso639-1 | en | - |
item.openairetype | Conference Object | - |
item.grantfulltext | none | - |
item.openairecristype | http://purl.org/coar/resource_type/c_18cf | - |
item.cerifentitytype | Publications | - |
item.fulltext | No Fulltext | - |
Appears in Collections: | Scopus İndeksli Yayınlar Koleksiyonu / Scopus Indexed Publications Collection WoS İndeksli Yayınlar Koleksiyonu / WoS Indexed Publications Collection |
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