Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.11851/12487
Full metadata record
DC FieldValueLanguage
dc.contributor.authorTugrul, Yahya Can-
dc.contributor.authorYaglikci, A. Giray-
dc.contributor.authorYuksel, Ismail Emir-
dc.contributor.authorOlgun, Ataberk-
dc.contributor.authorCanpolat, Oguzhan-
dc.contributor.authorBostanci, Nisa-
dc.contributor.authorMutlu, Onur-
dc.date.accessioned2025-05-10T19:34:54Z-
dc.date.available2025-05-10T19:34:54Z-
dc.date.issued2025-
dc.identifier.isbn9798331506483-
dc.identifier.isbn9798331506476-
dc.identifier.issn1530-0897-
dc.identifier.urihttps://doi.org/10.1109/HPCA61900.2025.00070-
dc.descriptionErgin, Oguz/0000-0003-2701-3787en_US
dc.description.abstractRead disturbance in modern DRAM chips is a widespread weakness that is used for breaking memory isolation, one of the fundamental building blocks of system security and privacy. RowHammer is a prime example of read disturbance in DRAM where repeatedly accessing (hammering) a row of DRAM cells (DRAM row) induces bitflips in physically nearby DRAM rows (victim rows). Unfortunately, shrinking technology node size exacerbates RowHammer and as such, significantly fewer accesses can induce bitflips in newer DRAM chip generations. To ensure robust DRAM operation, state-of-the-art mitigation mechanisms restore the charge in potential victim rows (i.e., they perform preventive refresh or charge restoration). With newer DRAM chip generations, these mechanisms perform preventive refresh more aggressively and cause larger performance, energy, or area overheads. Therefore, it is essential to develop a better understanding and in-depth insights into the preventive refresh to secure real DRAM chips at low cost. In this paper, our goal is to mitigate RowHammer at low cost by understanding the preventive refresh latency and the impact of reduced refresh latency on RowHammer. To this end, we present the first rigorous experimental study on the interactions between refresh latency and RowHammer characteristics in real DRAM chips. Our experimental characterization using 388 real DDR4 DRAM chips from three major manufacturers demonstrates that a preventive refresh latency can be significantly reduced (by 64%) at the expense of requiring slightly more (by 0.54%) preventive refreshes. To investigate the impact of reduced preventive refresh latency on system performance and energy efficiency, we reduce the preventive refresh latency and adjust the aggressiveness of existing RowHammer solutions by developing a new mechanism, Partial Charge Restoration for Aggressive Mitigation (PaCRAM). Our results show that by reducing the preventive refresh latency, PaCRAM reduces the performance and energy overheads induced by five state-of-the-art RowHammer mitigation mechanisms with small additional area overhead. Thus, PaCRAM introduces a novel perspective into addressing RowHammer vulnerability at low cost by leveraging our experimental observations. To aid future research, we open-source our PaCRAM implementation at https://github.com/CMU- SAFARI/PaCRAM.en_US
dc.description.sponsorshipGoogle Security and Privacy Research Award; Microsoft Swiss Joint Research Center; ETH Future Computing Laboratory; Google; Huawei; Intel; Microsoft; VMwareen_US
dc.description.sponsorshipWe thank the anonymous reviewers of HPCA 2025 (both main submission and artifact evaluation), MICRO 2024, and ISCA 2024 for the encouraging feedback. We thank the SAFARI Research Group members for valuable feedback and the stimulating scientific and intellectual environment. We acknowledge the generous gift funding provided by our industrial partners (especially Google, Huawei, Intel, Microsoft, VMware), which has been instrumental in enabling the research we have been conducting on read disturbance in DRAM since 2011 [3]. This work was also in part supported by the Google Security and Privacy Research Award, the Microsoft Swiss Joint Research Center, and the ETH Future Computing Laboratory (EFCL).en_US
dc.language.isoenen_US
dc.publisherIEEE Computer Socen_US
dc.relation.ispartof2025 International Symposium on High Performance Computer Architecture-HPCA-Annual -- MAR 01-05, 2025 -- Las Vegas, NVen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.titleUnderstanding Rowhammer Under Reduced Refresh Latency: Experimental Analysis of Real Dram Chips and Implications on Future Solutionsen_US
dc.typeConference Objecten_US
dc.relation.ispartofseriesInternational Symposium on High-Performance Computer Architecture-Proceedings-
dc.departmentTOBB University of Economics and Technologyen_US
dc.identifier.startpage867en_US
dc.identifier.endpage886en_US
dc.authoridErgin, Oguz/0000-0003-2701-3787-
dc.identifier.wosWOS:001494383800062-
dc.identifier.scopus2-s2.0-105003388361-
dc.identifier.doi10.1109/HPCA61900.2025.00070-
dc.authorwosidYüksel, İsmail Emir/Grj-1043-2022-
dc.authorwosidErgin, Oguz/E-5717-2010-
dc.relation.publicationcategoryKonferans Öğesi - Uluslararası - Kurum Öğretim Elemanıen_US
dc.identifier.scopusqualityN/A-
dc.identifier.wosqualityN/A-
dc.description.woscitationindexConference Proceedings Citation Index - Science-
item.languageiso639-1en-
item.openairetypeConference Object-
item.grantfulltextnone-
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
item.cerifentitytypePublications-
item.fulltextNo Fulltext-
Appears in Collections:Scopus İndeksli Yayınlar Koleksiyonu / Scopus Indexed Publications Collection
WoS İndeksli Yayınlar Koleksiyonu / WoS Indexed Publications Collection
Show simple item record



CORE Recommender

SCOPUSTM   
Citations

1
checked on Oct 18, 2025

Page view(s)

170
checked on Oct 20, 2025

Google ScholarTM

Check




Altmetric


Items in GCRIS Repository are protected by copyright, with all rights reserved, unless otherwise indicated.