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Title: Detecting Errors in Instructions with Bloom Filters
Authors: Atamaner, Mert
Ergin, Oğuz
Ottavi, Marco
Reviriego, Pedro
Keywords: fault tolerance
radiation hardening
transient faults
Issue Date: 2017
Publisher: IEEE
Source: Atamaner, M., Ergin, O., Ottavi, M., & Reviriego, P. (2017, October). Detecting errors in instructions with bloom filters. In 2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (pp. 1-4). IEEE.
Abstract: Bit flips on instructions may affect the execution of the processor depending on the Instruction Set Architecture (ISA) and the location of the flipped bits. Intrinsically, ISAs may detect bit upsets if the errors on the instructions produce exceptions that halt the execution. Previous works exploit this fact to improve the error detection capabilities of ISAs with an addition of simple encoding/decoding scheme to propagate any single bit error to the "most vulnerable bit" of the instructions in order to detect the error by crashing the system. Although it was proven that this approach significantly reduces the Silent Data Corruptions (SDC), as an error detection scheme, it is not practical since detection causes system crash. In this paper, we propose using a Bloom Filter (BF) along with the encode/decode scheme to detect soft errors without executing the erroneous instruction and thus avoiding system crash. The contents of the BF are those obtained by inserting the valid program instructions and can be computed at compile time. Then prior to execution, the contents are loaded into the BF. During execution, instructions are first checked on the BF and on a negative an error is detected as the instruction is not any of the ones in the program. A small number of false positives can occur for erroneous instructions (due to the nature of the BF) and may still be detected with the system crash as in previous works. Our approach has two main benefits. The first one is an increase in the error detection rate as the set of valid instructions is restricted to those used in the program allowing the detection of invalid instructions even if they do not lead to a system crash. The second one is that errors are detected before the crash. This is done at the cost of adding a small memory for the BF and some control logic that requires a low overhead. We evaluated this approach on binary files of the ARM Cortex M0 core. According to our findings, the BF is able to significantly improve the error detection rate.
Description: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (2017 : Cambridge, ENGLAND)
ISBN: 978-1-5386-0362-8
ISSN: 1550-5774
Appears in Collections:Bilgisayar Mühendisliği Bölümü / Department of Computer Engineering
Scopus İndeksli Yayınlar Koleksiyonu / Scopus Indexed Publications Collection
WoS İndeksli Yayınlar Koleksiyonu / WoS Indexed Publications Collection

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