Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.11851/2770
Title: Vortex Transitional Memory Developed with Nb 4-Layer, 10-kA/cm(2) Fabrication Process
Authors: Komura, Yuto
Tanaka, Masamitsu
Fujimaki, Akira
Nagasawa, Shuichi
Bozbey, Ali
Keywords: Fluxes
networks (circuits)
single flux
Issue Date: 2015
Publisher: IEEE
Source: Komura, Y., Tanaka, M., Nagasawa, S., Bozbey, A., and Fujimaki, A. (2015, July). Vortex Transitional Memory Developed with Nb 4-Layer, 10-kA/cm² Fabrication Process. In 2015 15th International Superconductive Electronics Conference (ISEC)(pp. 1-3). IEEE.
Abstract: We report random access memories (RAMs) based on vortex transitional (VT) memory cell developed with the newly developed AIST 10-kA/cm(2), Nb 4-layer fabrication process, called High-Speed Standard Process (HSTP). We obtained more effective mutual coupling structure by fully use of all the wiring layer, and successfully reduced the cell size to 25 mu m square, which indicated roughly 50% increase in density compared to the previous design. We reduced the critical currents of Josephson junctions and load resistance to be matched with driving circuitry. We tested the miniaturized VT memory cell, and obtained a sufficient margin width of similar to 15%, and also confirmed correct operations of the other components, including a latching driver and address decoder.
URI: https://hdl.handle.net/20.500.11851/2770
https://ieeexplore.ieee.org/document/7383489
ISBN: 978-1-4673-8348-6
Appears in Collections:Elektrik ve Elektronik Mühendisliği Bölümü / Department of Electrical & Electronics Engineering
Scopus İndeksli Yayınlar Koleksiyonu / Scopus Indexed Publications Collection
WoS İndeksli Yayınlar Koleksiyonu / WoS Indexed Publications Collection

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