Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.11851/2830
Title: Reduced CORDIC Based Logarithmic Convertor
Other Titles: İndirgemeli CORDIC Tabanlı Logaritma Çeviricisi
Authors: Helvacioğlu, Gülfem
Korucu, Ali Buğra
Alp, Yaşar Kemal
Kasnakoğlu, Coşku
Keywords: Logarithm
FPGA
CORDIC
signal processing
Issue Date: 2017
Publisher: IEEE
Source: Helvacioğlu, G., Alp, A. B. K. Y. K., and Kasnakoğlu, C. (2017, May). Reduced CORDIC based logarithmic convertor. In 2017 25th Signal Processing and Communications Applications Conference (SIU) (pp. 1-4). IEEE.
Abstract: In this work, a novel method Reduced CORDIC Based Logarithm Converter (RCBLC) is introduced for computing the specific-based logarithm of the binary values, and then the hardware architecture of RCBLC based on FPGA is analyzed in detail. Hardware architecture of RCBLC is implemented such that it enables logarithm conversion with both high output hit-sensitivity and low resource utilization. In addition to CORDIC method which includes only add-and-shift operations, using the rapid value reduction method provides an opportunity for calculating logarithm of a value more precise and lower resource utilization comparing to other methods. Thanks to the reduction method in it, RCBLC can provide wide operating input interval for logarithm conversion.
URI: https://hdl.handle.net/20.500.11851/2830
https://ieeexplore.ieee.org/document/7960483
ISBN: 978-1-5090-6494-6
ISSN: 2165-0608
Appears in Collections:Elektrik ve Elektronik Mühendisliği Bölümü / Department of Electrical & Electronics Engineering
Scopus İndeksli Yayınlar Koleksiyonu / Scopus Indexed Publications Collection
WoS İndeksli Yayınlar Koleksiyonu / WoS Indexed Publications Collection

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