Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.11851/3842
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dc.contributor.authorBolat, A.-
dc.contributor.authorCassano, L.-
dc.contributor.authorReviriego, P.-
dc.contributor.authorErgin, Oğuz-
dc.contributor.authorOttavid, M.-
dc.date.accessioned2020-10-22T16:40:33Z-
dc.date.available2020-10-22T16:40:33Z-
dc.date.issued2020-04
dc.identifier.citationBolat, A., Cassano, L., Reviriego, P., Ergin, O. and Ottavid, M. (2020, April). A Microprocessor Protection Architecture against Hardware Trojans in Memories. In 2020 15th Design & Technology of Integrated Systems in Nanoscale Era (DTIS) (pp. 1-6). IEEE.en_US
dc.identifier.isbn978-172815426-8
dc.identifier.urihttps://hdl.handle.net/20.500.11851/3842-
dc.identifier.urihttps://ieeexplore.ieee.org/document/9080961-
dc.description.abstractSoftware exploitable Hardware Trojan Horses (HWTs) have been currently inserted in commercial CPUs and, very recently, in memories. Such attacks may allow malicious users to run their own software or to gain unauthorized privileges over the system. Therefore, HWTs are nowadays considered a serious threat both from academy and industry. This paper presents a protection architecture meant to shield the communication between the CPU and the memory in a microprocessor-based system. The architecture aims at detecting the activation on HWTs infesting the instruction and data memories of the system. Our proposal relies on the use of Bloom Filters (BFs) that are included in ad-hoc designed checkers and integrated in the protection architecture. BFs guarantee zero false alarms and a small (and configurable) percentage of undetected alarms. We applied the protection architecture to a case study system based on a RISC-V microprocessor implemented on an FPGA and running a set of software benchmarks. Our proposal demonstrated to be able to detect more than 99% of possible HWTs activations with zero false alarms. We measured a lookup table overhead ranging from 0.68% up to 10.52% and a flip-flop overhead between 0.68% and 0.99%, and with no working frequency reduction. © 2020 IEEE.en_US
dc.language.isoenen_US
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.relation.ispartofProceedings - 2020 15th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2020en_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectBloom Filteren_US
dc.subjecthardware securityen_US
dc.subjectHardware Trojan Horsesen_US
dc.subjectMicroprocessor-based Systemen_US
dc.subjectRISC-Ven_US
dc.titleA Microprocessor Protection Architecture against Hardware Trojans in Memoriesen_US
dc.typeConference Objecten_US
dc.departmentFaculties, Faculty of Engineering, Department of Computer Engineeringen_US
dc.departmentFakülteler, Mühendislik Fakültesi, Bilgisayar Mühendisliği Bölümütr_TR
dc.authorid0000-0003-0784-8365-
dc.identifier.wosWOS:000588563400005en_US
dc.identifier.scopus2-s2.0-85085176704en_US
dc.institutionauthorErgin, Oğuz-
dc.identifier.doi10.1109/DTIS48698.2020.9080961-
dc.relation.publicationcategoryKonferans Öğesi - Uluslararası - Kurum Öğretim Elemanıen_US
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
item.grantfulltextnone-
item.fulltextNo Fulltext-
item.openairetypeConference Object-
item.cerifentitytypePublications-
item.languageiso639-1en-
crisitem.author.dept02.3. Department of Computer Engineering-
Appears in Collections:Bilgisayar Mühendisliği Bölümü / Department of Computer Engineering
Scopus İndeksli Yayınlar Koleksiyonu / Scopus Indexed Publications Collection
WoS İndeksli Yayınlar Koleksiyonu / WoS Indexed Publications Collection
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