Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.11851/4035
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dc.contributor.authorSalami, B.-
dc.contributor.authorOnural, E. B.-
dc.contributor.authorYüksel, I. E.-
dc.contributor.authorKoç, F.-
dc.contributor.authorErgin, Oğuz-
dc.contributor.authorCristal Kestelman, A.-
dc.contributor.authorÜnsal, O.-
dc.contributor.authorSarbazi-Azad, H.-
dc.contributor.authorMutlu, O.-
dc.date.accessioned2021-01-25T11:28:54Z
dc.date.available2021-01-25T11:28:54Z
dc.date.issued2020-07
dc.identifier.citationSalami, B., Onural, E. B., Yuksel, I. E., Koc, F., Ergin, O., Kestelman, A. C., ... and Mutlu, O. (2020). An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration. arXiv preprint arXiv:2005.03451.en_US
dc.identifier.isbn978-172815809-9
dc.identifier.urihttps://ieeexplore.ieee.org/document/9153393-
dc.identifier.urihttps://hdl.handle.net/20.500.11851/4035-
dc.description.abstractWe empirically evaluate an undervolting technique, i.e., underscaling the circuit supply voltage below the nominal level, to improve the power-efficiency of Convolutional Neural Network (CNN) accelerators mapped to Field Programmable Gate Arrays (FPGAs). Undervolting below a safe voltage level can lead to timing faults due to excessive circuit latency increase. We evaluate the reliability-power trade-off for such accelerators. Specifically, we experimentally study the reduced-voltage operation of multiple components of real FPGAs, characterize the corresponding reliability behavior of CNN accelerators, propose techniques to minimize the drawbacks of reduced-voltage operation, and combine undervolting with architectural CNN optimization techniques, i.e., quantization and pruning. We investigate the effect ofenvironmental temperature on the reliability-power trade-off of such accelerators. We perform experiments on three identical samples of modern Xilinx ZCU102 FPGA platforms with five state-of-the-art image classification CNN benchmarks. This approach allows us to study the effects of our undervolting technique for both software and hardware variability. We achieve more than 3X power-efficiency (GOPs/W ) gain via undervolting. 2.6X of this gain is the result of eliminating the voltage guardband region, i.e., the safe voltage region below the nominal level that is set by FPGA vendor to ensure correct functionality in worst-case environmental and circuit conditions. 43% of the power-efficiency gain is due to further undervolting below the guardband, which comes at the cost of accuracy loss in the CNN accelerator. We evaluate an effective frequency underscaling technique that prevents this accuracy loss, and find that it reduces the power-efficiency gain from 43% to 25%. © 2020 IEEE.en_US
dc.language.isoenen_US
dc.publisherInstitute of Electrical and Electronics Engineers Inc.en_US
dc.relation.ispartofProceedings - 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networen_US
dc.rightsinfo:eu-repo/semantics/openAccessen_US
dc.subjectObject Detection en_US
dc.subject CNN en_US
dc.subject IOUen_US
dc.titleAn Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Accelerationen_US
dc.typeConference Objecten_US
dc.departmentFaculties, Faculty of Engineering, Department of Computer Engineeringen_US
dc.departmentFakülteler, Mühendislik Fakültesi, Bilgisayar Mühendisliği Bölümütr_TR
dc.identifier.startpage138
dc.identifier.endpage149
dc.relation.ec[779656]en_US
dc.authorid0000-0003-0784-8365-
dc.identifier.wosWOS:000617924900012en_US
dc.identifier.scopus2-s2.0-85086284016en_US
dc.institutionauthorErgin, Oğuz-
dc.identifier.doi10.1109/DSN48063.2020.00032-
dc.relation.publicationcategoryKonferans Öğesi - Uluslararası - Kurum Öğretim Elemanıen_US
dc.relation.otherWe thank the anonymous DSN2020 reviewers for their feedback and comments, as well as Dr. Long Wang, who helped us with shepherding. Also, we thank Dr. Konstantinos Parasyris for his in-depth review of the first version of this paper. The work done for this paper was partially supported by a HiPEAC Collaboration Grant funded by the H2020 HiPEAC Project under grant agreement No. 779656. The research leading to these results has received funding from the European Union’s Horizon 2020 Programme under the LEGaTO Project (www.legato-project.eu), grant agreement No. 780681.en_US
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
item.grantfulltextnone-
item.fulltextNo Fulltext-
item.openairetypeConference Object-
item.cerifentitytypePublications-
item.languageiso639-1en-
crisitem.author.dept02.3. Department of Computer Engineering-
Appears in Collections:Bilgisayar Mühendisliği Bölümü / Department of Computer Engineering
Scopus İndeksli Yayınlar Koleksiyonu / Scopus Indexed Publications Collection
WoS İndeksli Yayınlar Koleksiyonu / WoS Indexed Publications Collection
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