Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.11851/4036
Title: A Novel FPGA-Based High Throughput Accelerator for Binary Search Trees
Authors: Melikoğlu, Öykü
Ergin, Oğuz
Salami, B.
Pavon, J.
Ünsal, O.
Cristal, A.
Keywords: Binary Search Tree (BST)
FPGA
Hardware Accelerator
Parallel Search
Issue Date: Jul-2019
Publisher: Institute of Electrical and Electronics Engineers Inc.
Source: Melikoglu, O., Ergin, O., Salami, B., Pavon, J., Unsal, O., and Cristal, A. (2019). A novel fpga-based high throughput accelerator for binary search trees. arXiv preprint arXiv:1912.01556.
Abstract: This paper presents a deeply pipelined and massively parallel Binary Search Tree (BST) accelerator for Field Programmable Gate Arrays (FPGAs). Our design relies on the extremely parallel on-chip memory, or Block RAMs (BRAMs) architecture of FPGAs. To achieve significant throughput for the search operation on BST, we present several novel mechanisms including tree duplication as well as horizontal, duplicated, and hybrid (horizontal-vertical) tree partitioning. Also, we present efficient techniques to decrease the stalling rates that can occur during the parallel tree search. By combining these techniques and implementations on Xilinx Virtex-7 VC709 platform, we achieve up to 8X throughput improvement gain in comparison to the baseline implementation, i.e., a fully-pipelined FPGA-based accelerator. © 2019 IEEE.
URI: https://hdl.handle.net/20.500.11851/4036
https://ieeexplore.ieee.org/document/9188158
ISBN: 978-172814484-9
Appears in Collections:Bilgisayar Mühendisliği Bölümü / Department of Computer Engineering
Scopus İndeksli Yayınlar Koleksiyonu / Scopus Indexed Publications Collection

Show full item record

CORE Recommender

SCOPUSTM   
Citations

1
checked on Sep 23, 2022

Page view(s)

94
checked on Dec 26, 2022

Google ScholarTM

Check

Altmetric


Items in GCRIS Repository are protected by copyright, with all rights reserved, unless otherwise indicated.