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|Title:||Instruction Packing: Toward Fast and Energy-Efficient Instruction Scheduling||Authors:||Sharkey, J. J.
Ponomarev, D. V.
|Issue Date:||2006||Abstract:||Traditional dynamic scheduler designs use one issue queue entry per instruction, regardless of the actual number of operands actively involved in the wakeup process. We propose Instruction Packing—a novel microarchitectural technique that reduces both delay and power consumption of the issue queue by sharing the associative part of an issue queue entry between two instructions, each with, at most, one nonready register source operand at the time of dispatch. Our results show that this technique results in 40% reduction of the IQ power and 14% reduction in scheduling delay with negligible IPC degradations. © 2006, ACM. All rights reserved.||URI:||https://doi.org/10.1145/1138035.1138037
|Appears in Collections:||Bilgisayar Mühendisliği Bölümü / Department of Computer Engineering|
Scopus İndeksli Yayınlar Koleksiyonu / Scopus Indexed Publications Collection
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