Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.11851/5790
Title: Instruction Packing: Toward Fast and Energy-Efficient Instruction Scheduling
Authors: Sharkey, J. J.
Ponomarev, D. V.
Ghose, K.
Ergin, Oğuz
Keywords: Instruction packing
Issue queue
Low power
Performance
Power
Superscalar Processors
Issue Date: 2006
Abstract: Traditional dynamic scheduler designs use one issue queue entry per instruction, regardless of the actual number of operands actively involved in the wakeup process. We propose Instruction Packing—a novel microarchitectural technique that reduces both delay and power consumption of the issue queue by sharing the associative part of an issue queue entry between two instructions, each with, at most, one nonready register source operand at the time of dispatch. Our results show that this technique results in 40% reduction of the IQ power and 14% reduction in scheduling delay with negligible IPC degradations. © 2006, ACM. All rights reserved.
URI: https://doi.org/10.1145/1138035.1138037
https://hdl.handle.net/20.500.11851/5790
ISSN: 1544-3566
Appears in Collections:Bilgisayar Mühendisliği Bölümü / Department of Computer Engineering
Scopus İndeksli Yayınlar Koleksiyonu / Scopus Indexed Publications Collection

Show full item record

CORE Recommender

SCOPUSTM   
Citations

8
checked on Sep 23, 2022

Page view(s)

28
checked on Dec 26, 2022

Google ScholarTM

Check

Altmetric


Items in GCRIS Repository are protected by copyright, with all rights reserved, unless otherwise indicated.