Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.11851/7378
Title: Reducing Parity Generation Latency through Input Value Aware Circuits
Authors: Osmanlıoğlu, Yusuf
Koçberber, Y. Onur
Ergin, Oğuz
Keywords: Error Correcting Codes (ECC)
Narrow Values
Parity Generation
Issue Date: 2009
Publisher: Assoc Computing Machinery
Source: 19th Great Lakes Symposium on VLSI 2009 -- MAY 10-12, 2009 -- Braintree, MA
Abstract: Soft errors caused by cosmic particles and radiation emitted by the packaging are an important problem in contemporary microprocessors. Parity bits are used to detect single bit errors that occur in the storage components. In order to implement parity logic, multiple levels of XOR gates are used and these XOR trees are known to have high delay. Many produced and consumed values inside a processor hold consecutive zeros and ones in their upper order bits. These values can be represented with less number of bits and hence are termed narrow. In this paper we propose a parity generator circuit design that is capable of generating the parity if the input value is narrow. We show that parity can be generated faster than a regular XOR tree implementation using our design for the values that can be represented using fewer bits.
URI: https://hdl.handle.net/20.500.11851/7378
ISBN: 978-1-60558-522-2
Appears in Collections:Bilgisayar Mühendisliği Bölümü / Department of Computer Engineering
Scopus İndeksli Yayınlar Koleksiyonu / Scopus Indexed Publications Collection
WoS İndeksli Yayınlar Koleksiyonu / WoS Indexed Publications Collection

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