Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.11851/8598
Title: Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches
Authors: Arikan, Kerem
Palumbo, Alessandro
Cassano, Luca
Reviriego, Pedro
Pontarelli, Salvatore
Bianchi, Giuseppe
Ergin, Oğuz
Keywords: Microarchitecture
Security
Microprocessors
Hazards
Codes
Hardware
Timing
Embedded systems
hardware security
microarchitectural attacks
microprocessors
RISC-V
Side-Channel Attacks
Issue Date: 2022
Publisher: IEEE-Inst Electrical Electronics Engineers Inc
Source: Arikan, K., Palumbo, A., Cassano, L., Reviriego, P., Pontarelli, S., Bianchi, G., ... & Ottavi, M. (2022). Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches. IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
Abstract: The continuous quest for performance pushed processors to incorporate elements such as multiple cores, caches, acceleration units, or speculative execution that make systems very complex. On the other hand, these features often expose unexpected vulnerabilities that pose new challenges. For example, the timing differences introduced by caches or speculative execution can be exploited to leak information or detect activity patterns. Protecting embedded systems from existing attacks is extremely challenging, and it is made even harder by the continuous rise of new microarchitectural attacks (e.g., the Spectre and Orchestration attacks). In this article, we present a new approach based on count-min sketches for detecting microarchitectural attacks in the microprocessors featured by embedded systems. The idea is to add to the system a security checking module (without modifying the microprocessor under protection) in charge of observing the fetched instructions and identifying and signaling possible suspicious activities without interfering with the nominal activity of the system. The proposed approach can be programmed at design time (and reprogrammed after deployment) in order to always keep updated the list of the attacks that the checker is able to identify. We integrated the proposed approach in a large RISC-V core, and we proved its effectiveness in detecting several versions of the Spectre, Orchestration, Rowhammer, and Flush + Reload attacks. In its best configuration, the proposed approach has been able to detect 100% of the attacks, with no false alarms and introducing about 10% area overhead, about 4% power increase, and without working frequency reduction.
URI: https://doi.org/10.1109/TVLSI.2022.3171810
https://hdl.handle.net/20.500.11851/8598
ISSN: 1063-8210
1557-9999
Appears in Collections:Bilgisayar Mühendisliği Bölümü / Department of Computer Engineering
Scopus İndeksli Yayınlar Koleksiyonu / Scopus Indexed Publications Collection
WoS İndeksli Yayınlar Koleksiyonu / WoS Indexed Publications Collection

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