Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.11851/8868
Title: DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators
Authors: Bostanci, F. Nisa
Olgun, Ataberk
Ergin, Oğuz
Yaglikci, A. Giray
Kim, Jeremie S.
Hassan, Hasan
Mutlu, Onur
Keywords: Latency Dram
Flash Memory
Rethinking
Bandwidth
Fair
Issue Date: 2022
Publisher: IEEE Computer Soc
Abstract: Random number generation is an important task in a wide variety of critical applications including cryptographic algorithms, scientific simulations, and industrial testing tools. True Random Number Generators (TRNGs) produce cryptographically secure truly random data by sampling a physical entropy source that typically requires custom hardware and suffers from long latency. To enable high-bandwidth and low-latency TRNGs on widely-available commodity devices, recent works propose hardware TRNGs that generate random numbers using commodity DRAM as an entropy source. Although prior works demonstrate promising TRNG mechanisms using DRAM, practical integration of such mechanisms into real systems poses various challenges. We identify three key challenges for using DRAM-based TRNGs in current systems: (1) generating random numbers with DRAM-based TRNGs can degrade overall system performance by slowing down concurrently-running applications due to the interference between RNG and regular memory operations in the memory controller (i.e., RNG interference), (2) this RNG interference can degrade system fairness by causing unfair prioritization of applications that intensively use random numbers (i.e., RNG applications), and (3) RNG applications can experience significant slowdown due to the high latency of DRAM-based TRNGs. To address these challenges, we propose DR-STRaNGe, an end-to-end system design for DRAM-based TRNGs that (1) reduces the RNG interference by separating RNG requests from regular memory requests in the memory controller, (2) improves fairness across applications with an RNG-aware memory request scheduler, and (3) hides the large TRNG latencies using a random number buffering mechanism combined with a new DRAM idleness predictor that accurately identifies idle DRAM periods. We evaluate DR-STRaNGe using a comprehensive set of 186 multi programmed workloads. Compared to an RNG-oblivious baseline system, DR-STRaNGe improves the performance of non-RNG and RNG applications on average by 17.9% and 25.1%, respectively. DR-STRaNGe improves system fairness by 32.1% on average when generating random numbers at a 5 Gb/s throughput. DR-STRaNGe reduces energy consumption by 21% compared to the RNG-oblivious baseline design by reducing the time spent for RNG and non-RNG memory accesses by 15.8%.
Description: 28th Annual IEEE International Symposium on High-Performance Computer Architecture (HPCA) -- APR 02-06, 2022 -- ELECTR NETWORK
URI: https://doi.org/10.1109/HPCA53966.2022.00087
https://hdl.handle.net/20.500.11851/8868
ISBN: 978-1-6654-2027-3
ISSN: 1530-0897
Appears in Collections:Scopus İndeksli Yayınlar Koleksiyonu / Scopus Indexed Publications Collection
WoS İndeksli Yayınlar Koleksiyonu / WoS Indexed Publications Collection

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