Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.11851/9249
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dc.contributor.authorOlgun, A.-
dc.contributor.authorLuna, J.G.-
dc.contributor.authorKanellopoulos, K.-
dc.contributor.authorSalami, B.-
dc.contributor.authorHassan, H.-
dc.contributor.authorErgin, Oğuz-
dc.contributor.authorMutlu, O.-
dc.date.accessioned2022-11-30T19:37:38Z-
dc.date.available2022-11-30T19:37:38Z-
dc.date.issued2022-
dc.identifier.isbn9781665466059-
dc.identifier.issn2159-3469-
dc.identifier.urihttps://doi.org/10.1109/ISVLSI54635.2022.00059-
dc.identifier.urihttps://hdl.handle.net/20.500.11851/9249-
dc.descriptionIEEE;IEEE Computer Society;Research and Innovation Center of Excellence (KOIOS);Technical Committee on VLSI (TCVLSI);University of Cyprusen_US
dc.description2022 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2022 -- 4 July 2022 through 6 July 2022 -- 183621en_US
dc.description.abstractDRAM-based main memory is used in nearly all computing systems as a major component. Modern memory-intensive workloads have increasing memory bandwidth, latency, and capacity requirements. However, DRAM vendors often prioritize memory capacity scaling over latency and bandwidth [1]-[4]. As a result, main memory is an increasingly worsening bottleneck in computing systems [3,5-9]. © 2022 IEEE.en_US
dc.description.sponsorshipSemiconductor Research Corporation, SRCen_US
dc.description.sponsorshipWe thank the SAFARI Research Group members for valuable feedback and the stimulating intellectual environment they provide. We acknowledge the generous gifts provided by our industrial partners, including Google, Huawei, Intel, Microsoft, and VMware. We acknowledge support from the Semiconductor Research Corporation and the ETH Future Computing Laboratory.en_US
dc.language.isoenen_US
dc.publisherIEEE Computer Societyen_US
dc.relation.ispartofProceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSIen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectBandwidthen_US
dc.subjectField programmable gate arrays (FPGA)en_US
dc.subjectBandwidth requirementen_US
dc.subjectCapacity requirementen_US
dc.subjectCapacity scalingen_US
dc.subjectComputing systemen_US
dc.subjectEnd to enden_US
dc.subjectMain-memoryen_US
dc.subjectMemory bandwidthsen_US
dc.subjectMemory capacityen_US
dc.subjectMemory latenciesen_US
dc.subjectDynamic random access storageen_US
dc.titlePiDRAM: An FPGA-based Framework for End-to-end Evaluation of Processing-in-DRAM Techniquesen_US
dc.typeConference Objecten_US
dc.identifier.volume2022-Julyen_US
dc.identifier.startpage267en_US
dc.identifier.endpage272en_US
dc.identifier.wosWOS:000886230500046en_US
dc.identifier.scopus2-s2.0-85140904672en_US
dc.institutionauthorErgin, Oguz-
dc.institutionauthorErgin, Oğuz-
dc.identifier.doi10.1109/ISVLSI54635.2022.00059-
dc.authorscopusid57222238840-
dc.authorscopusid57211567599-
dc.authorscopusid57211567864-
dc.authorscopusid56029413900-
dc.authorscopusid57189066886-
dc.authorscopusid6603141208-
dc.authorscopusid16043006700-
dc.relation.publicationcategoryKonferans Öğesi - Uluslararası - Kurum Öğretim Elemanıen_US
dc.ozel2022v3_Editen_US
item.cerifentitytypePublications-
item.languageiso639-1en-
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
item.openairetypeConference Object-
item.fulltextNo Fulltext-
item.grantfulltextnone-
crisitem.author.dept02.3. Department of Computer Engineering-
Appears in Collections:Bilgisayar Mühendisliği Bölümü / Department of Computer Engineering
Scopus İndeksli Yayınlar Koleksiyonu / Scopus Indexed Publications Collection
WoS İndeksli Yayınlar Koleksiyonu / WoS Indexed Publications Collection
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