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Title: HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips
Authors: Giray, Yaglikci, A.
Olgun, A.
Patel, M.
Luo, H.
Hassan, H.
Orosa, L.
Ergin, Oğuz
Keywords: DRAM
memory access latency
memory controller
Dynamic random access storage
Failure (mechanical)
Memory architecture
Data loss
DRAM cells
DRAM chips
Memory access
Memory access latency
Memory controller
Systems performance
Technology nodes
Chemical activation
Issue Date: 2022
Publisher: IEEE Computer Society
Abstract: DRAM is the building block of modern main memory systems. DRAM cells must be periodically refreshed to prevent data loss. Refresh operations degrade system performance by interfering with memory accesses. As DRAM chip density increases with technology node scaling, refresh operations also increase be-cause: 1) the number of DRAM rows in a chip increases; and 2) DRAM cells need additional refresh operations to mitigate bit failures caused by RowHammer, a failure mechanism that becomes worse with technology node scaling. Thus, it is critical to enable refresh operations at low performance overhead. To this end, we propose a new operation, Hidden Row Activation (HiRA), and the HiRA Memory Controller (HiRA-MC) to perform HiRA operations. HiRA hides a refresh operation's latency by refreshing a row concurrently with accessing or refreshing another row within the same bank. Unlike prior works, HiRA achieves this parallelism without any modifications to off-the-shelf DRAM chips. To do so, it leverages the new observation that two rows in the same bank can be activated without data loss if the rows are connected to different charge restoration circuitry. We experimentally demonstrate on 56 real off-the-shelf DRAM chips that HiRA can reliably parallelize a DRAM row's refresh operation with refresh or activation of any of the 32% of the rows within the same bank. By doing so, HiRA reduces the overall latency of two refresh operations by 51.4%. HiRA-MC modifies the memory request scheduler to perform HiRA when a refresh operation can be performed concurrently with a memory access or another refresh. Our system-level evaluations show that HiRA-MC increases system performance by 12.6% and 3.73× as it reduces the performance degradation due to periodic refreshes and refreshes for RowHammer protection (preventive refreshes), respectively, for future DRAM chips with increased density and RowHammer vulnerability. © 2022 IEEE.
Description: aws;et al.;Futurewei Technologies;IBM;Intel;Northwestern Engineering
55th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2022 -- 1 October 2022 through 5 October 2022 -- 183812
ISBN: 9781665462723
ISSN: 1072-4451
Appears in Collections:Bilgisayar Mühendisliği Bölümü / Department of Computer Engineering
Scopus İndeksli Yayınlar Koleksiyonu / Scopus Indexed Publications Collection

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