Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.11851/9249
Title: PiDRAM: An FPGA-based Framework for End-to-end Evaluation of Processing-in-DRAM Techniques
Authors: Olgun, A.
Luna, J.G.
Kanellopoulos, K.
Salami, B.
Hassan, H.
Ergin, Oğuz
Mutlu, O.
Keywords: Bandwidth
Field programmable gate arrays (FPGA)
Bandwidth requirement
Capacity requirement
Capacity scaling
Computing system
End to end
Main-memory
Memory bandwidths
Memory capacity
Memory latencies
Dynamic random access storage
Issue Date: 2022
Publisher: IEEE Computer Society
Abstract: DRAM-based main memory is used in nearly all computing systems as a major component. Modern memory-intensive workloads have increasing memory bandwidth, latency, and capacity requirements. However, DRAM vendors often prioritize memory capacity scaling over latency and bandwidth [1]-[4]. As a result, main memory is an increasingly worsening bottleneck in computing systems [3,5-9]. © 2022 IEEE.
Description: IEEE;IEEE Computer Society;Research and Innovation Center of Excellence (KOIOS);Technical Committee on VLSI (TCVLSI);University of Cyprus
2022 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2022 -- 4 July 2022 through 6 July 2022 -- 183621
URI: https://doi.org/10.1109/ISVLSI54635.2022.00059
https://hdl.handle.net/20.500.11851/9249
ISBN: 9781665466059
ISSN: 2159-3469
Appears in Collections:Scopus İndeksli Yayınlar Koleksiyonu / Scopus Indexed Publications Collection

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