02.3. Department of Computer Engineering
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Issue Date | Title | Author(s) | |
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1 | 2022 | Composable Cachelets: Protecting Enclaves from Cache Side-Channel Attacks | Townley, Daniel; Arikan, Kerem; Liu, Yu David; Ponomarev, Dmitry; Ergin, Oğuz |
2 | 2023 | DEV-PIM: Dynamic Execution Validation with Processing-in-Memory | Bolata, Alperen; Tuğrul, Yahya Can; Çelik, Seyyid Hikmet; Sezer, Şakir; Ottavi, Marco; Ergin, Oğuz |
3 | 2022 | DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators | Bostanci, F. Nisa; Olgun, Ataberk; Orosa, Lois; Yaglikci, A. Giray; Kim, Jeremie S.; Hassan, Hasan; Mutlu, Onur; Ergin, Oğuz |
4 | 2022 | ERIC: An Efficient and Practical Software Obfuscation Framework | Bolat, Alperen; Celik, Seyyid Hikmet; Olgun, Ataberk; Ergin, Oğuz ; Ottavi, Marco |
5 | Jul-2020 | An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration | Salami, B.; Onural, E. B.; Yüksel, I. E.; Koç, F.; Ergin, Oğuz ; Cristal Kestelman, A.; Ünsal, O.; Sarbazi-Azad, H.; Mutlu, O. |
6 | 2022 | HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips | Giray, Yaglikci, A.; Olgun, A.; Patel, M.; Luo, H.; Hassan, H.; Orosa, L.; Ergin, Oğuz |
7 | Apr-2020 | A Microprocessor Protection Architecture against Hardware Trojans in Memories | Bolat, A.; Cassano, L.; Reviriego, P.; Ergin, Oğuz ; Ottavid, M. |
8 | 2022 | PiDRAM: An FPGA-based Framework for End-to-end Evaluation of Processing-in-DRAM Techniques | Olgun, A.; Luna, J.G.; Kanellopoulos, K.; Salami, B.; Hassan, H.; Ergin, Oğuz ; Mutlu, O. |
9 | 2021 | QUAC-TRNG: High Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips | Olgun, Ataberk; Patel, Minesh; Yağlıkçı, A. Giray; Luo, Haocong; Ergin, Oğuz ; Bostancı, F. Nisa; Vijaykumar, Nandita |